1. Field of the Invention
The present invention relates to a level conversion circuit, more particularly, to a circuit for converting an emitter-coupled logic (ECL) logic level into a complementary metal oxide semiconductor (CMOS) logic level.
Bipolar CMOS (Bi-CMOS) semiconductor integrated circuit devices are excellent in high speed operation and low power dissipation applications. Nevertheless, a further decrease in power dissipation has been recently demanded in Bi-CMOS. Accordingly, a further decrease in power dissipation of a level conversion circuit, which is employed in a Bi-CMOS semiconductor integrated circuit device to convert an ECL logic level into a CMOS logic level, has also been demanded.
2. Description of the Related Art
A known level conversion circuit of the above type generally comprises an ECL logic circuit having a pair of emitter-coupled transistors (current switch circuit) responsive to an input signal of ECL logic level, an output transistor coupled to a collector of at least one of the emitter-coupled transistors, and a current control circuit comprising a current mirror circuit for controlling a current flowing through the output of the output transistor, the circuit carrying out a level conversion of the input signal to a CMOS level control signal.
Since the level conversion circuit of this type employs a current mode logic in both the ECL logic circuit and the current control circuit, it can achieve high speed operation. However, some current always flows in both of the circuits and thus the power dissipation is relatively high.
Especially, when the level conversion circuit is used in an apparatus or system having a relatively long stand-by time during which it resides in an inoperative state, the power dissipation thereof is even greater. Accordingly, there is an even greater need to decrease the power dissipation of the entire circuit.
To this end, an idea that power supply voltages fed to the apparatus or system are cut off in the stand-by state has been conceived. However, when the apparatus or system is brought to its working state from its stand-by state and thus powered ON, a problem occurs in that the operations of each circuit supplied with the power supply voltages are delayed. This is an obstacle to high speed operation and thus is not desired.
The problems in the prior art will be explained in detail later in contrast with the preferred embodiments of the present invention.